design a simple serial pattern recognizer for a new product.Your boss wants you to design a simple serial pattern recognizer for a new product. The unit has a 1-bit input that is sampled on every rising edge of a clock. The output is a single bit that goes to 1 for a single clock cycle when the 3-bit pattern “101” is detected and is set to zero at all other times. You decide that a simple Moore FSM to keep track of the input sequences is the simplest way to implement the recognizer (BTW it is). A state transition diagram is provided. You will also require a reset input to start everything at a known beginning state. Design your FSM using Verilog on Quartus and Create a Verilog testbench file