>logisim- implement cacheDont accept the task unless you are sure that you can implement it. implement Cache (Link below) using Logisim. Theres two already made circuits one is called cache.cir which is the circuit that You will write your solution inside. The other file Cachegrader.circ you use it to check whether your solution is correct. Link for Logisim evolution: you may only use Unless a problem specifies otherwise. Implement a Cache that meets the specifications below. All of the inputs will only be valid during the SINGLE clock cycle that your Cache says it is Ready. This means that you will have to save your inputs if you need them beyond that first clock cycle. The only exception to this is LineFromMem. It will be valid as long as you say you want to read from memory. If you aren’t reading from memory LineFromMem will be EEE… and Red (an Error). Don’t worry about this it is normal behavior. As soon as your request to read from memory it will be the value at MemAddress. Our Memory is going to be Block Addressable instead of Byte Addressable. This means that each block has an address instead of each byte. This enables you to read a block from/write a block to memory in a single clock cycle which should help simplify your design a little. It should be pretty easy to figure out which bits to drop to form MemAddress. Hint: it is bits that help you pick out the byte within a block. Your circuit must be able to complete a Read/Write request within 10 clock cycles. If you take longer than 10 clock cycles the tester will automatically advance to the next case. This will cause your Cache to start to “desync” from the tester and so will get everything wrong if you are taking too long. You can certainly finish in less than 10 clock cycles I only took 7 but I’ve seen students get as low as 2. Anytime your reset a test case you must RELOAD the RAM! The RAM is the only one that has to be reloaded. The ROM’s will maintain the last value you put in them. At the bottom of the the main circuit you will find probes that show your circuit’s inputs outputs answers how many reads you got correct how many times you said you hit and how many misses(memory reads) you had. This is a good place to look when you are debugging to get a high level overview of what your cache is doing. If you open the solution files in a text editor you will find what the correct values for all of the stats should be for that test case. I recommend running the test cases in the following If you want to make your own test you can use cache_test_maker.py to create your own tests. It should be fairly easy to follow the documentation inside if you feel like using it. Your score is calculated as num_correct_read_values – abs(num_correct_read_value – number_of_reads_you_got_correct) + num_correct_hits – abs(num_correct_hits – your_number_of_hits) + num_correct_misses – abs(num_correct_misses – your_number_of_misses). Essentially you lose points for every value you are off from the right answers. https://github.com/NoahRoseLedesma/CacheHitDetector A file named Cache.circ with your solution in the implementation subcircuit